Non-volatile memory devices maintain data even during power-off by using ferroelectric materials. The ferroelectric materials have hysteresis properties, e.g., PZT. Recent work with ferroelectric-based random access memory devices (FRAM) has shown many advantages over other memory technologies. For example, FRAMs operate at high speeds and low voltages. FRAMs do not require an overly complicated construction and FRAMs allow non-volatile storage. The operational speed of FRAM is typically dependent on the time it takes the ferroelectric material to reverse its polarization. The polarization reverse speed depends on a square measurement of capacitor plates and the thickness of the ferroelectric thin film used to form the FRAM as well as the voltage applied to the device. Experiments have shown that FRAMs are far faster than other non-volatile technologies such as EEPROMs or flash memory devices.
FIG. 1 is a block diagram of a conventional FRAM. Referring to FIG. 1, the FRAM device FIG. comprises a memory cell array 10, a row selector circuit 20, a row address latch circuit 30, a column address latch circuit 40, a column selector circuit 50, a chip enable buffer circuit 60, an input/output control circuit 70, a sense amplifier circuit 80, a data output buffer & write driver circuit 90, an input/output latch circuit 100, and a control circuit 110.
FIG. 2 is a timing diagram associated with a read operation of the FRAM shown in FIG. 1. When an external chip enable signal XCEB transitions from high to low, the chip enable buffer circuit 60 activates a high chip enable flag signal ICE. At this time, the row and column address latch circuits 30 and 40 latch corresponding valid addresses in response to the chip enable flag signal ICE. The row selector circuit 20 activates a word line (e.g., WL0) and a plate line (e.g., PL0) in response to a row address RAi/RAiB (i is, e.g., any integer greater than or equal to 1) latched in the row address latch circuit 30. Activation of the plate line PL0 cause charge sharing between a ferroelectric capacitor and a bit line.
The control circuit 110 activates a sense amplification enable signal SAEN in response to a flag signal PLFLAG indicating that a plate line is selected. This enables the sense amplifier circuit 80 to sense and amplify voltages on each bit line. The data output buffer circuit 90 externally outputs, as read data, the amplified voltages on columns or bit lines. The column selector circuit 50 selects the columns, and the input/output latch circuit 100 externally provides the read data. After the external chip enable signal XCEB is deactivated high, the chip enable flag signal ICE and the activated word line are sequentially deactivated responsive to the sense amplification enable signal SAEN.
FIG. 3 is a timing diagram showing a write operation of the FRAM shown in FIG. 1. Referring to FIG. 3, the write operation is the same as the read operation described above, except that data to be stored in the memory cell array 10 is transferred onto selected bit lines through the input/output latch circuit 110, the write driver circuit 90, and the column selector circuit 50. One disadvantage associated with the conventional FRAM device is that it does not satisfy an asynchronous operating condition of a memory which adopts an address transition detecting manner. Such a memory requires that a write operation is carried out successively after a read/write operation (asynchronous operation). As illustrated in FIGS. 2 and 3, the conventional FRAM device latches an address when an external chip enable signal XCEB is active low, and performs a read/write operation using the latched address. That is, the conventional FRAM device performs a read/write operation in synchronization with a transition of the external chip enable signal XCEB.
Hence, it is not possible to perform a read/write operation while the external chip enable signal XCEB is active low (or before the external chip enable signal XCEB is inactive high).